Fast CMOS static random access memories (SRAMs) have become increasingly important in computer systems which require high speed and low standby current. A write architecture block diagram for a conventional SRAM 10 is illustrated in FIG. 1. One of multiple input data signals (Data.sub.-- In.sub.-- Pad) from an input/output (I/O) pad 12 are applied to the memory device and received at data buffer circuitry 14. Data buffer circuitry 14 is part of a data input path for the memory device and may receive a TTL-compatible signal Data.sub.-- In.sub.-- Pad from I/O pad 12. Within the data buffer circuitry 14, the Data.sub.-- In.sub.-- Pad signal may be presented to a voltage level converter which converts the TTL signals to CMOS-compatible signals for use in the memory device. The data buffer circuitry 14, which may also contain delay circuits to adjust the timing of the data signal with respect to an internal write control signal, generates a Data.sub.-- In signal (generally, but not necessarily, a true and complement pair) which further propagates through an internal data input bus 16.
An Internal.sub.-- Write signal may be generated from the write enable (WE) and/or chip enable (CE) signals presented to the memory device 10. For example, using write control logic 18, signal Internal.sub.-- Write is developed from the WE and CE signals. Signal Internal.sub.-- Write is subsequently applied to the input of data write driver 20. A faster and/or wider internal write signal (or simply components of it, e.g., even WE and/or CE) may also gate the data input path at the data buffer 14 level (dashed line in FIG. 1).
At data write driver 20, signal Data.sub.-- In is combined with (e.g., gated by) signal Internal.sub.-- Write to produce internal write signals datawrt0 and datawrt1 which are logic complements during write operations. The internal write signals datawrt0 and datawrt1 are applied to the appropriate bitlines of memory device 10 through a data write bus 22 and a bitline interface to write data into selected individual memory cells.
For those memory devices which are organized into a number of groups of memory cells, each column (a-p) within a group of cells will have a corresponding bitline interface 24a-24p. The bitline interfaces 24a-24p are typically activated in response to group and column select signals Group/Column(0)-Group/Column(n), generated from address signals A.sub.0 -A.sub.m (e.g., from a system address bus) by a group and column select logic block 26. Thus, bitline interface 24a corresponds to group and column select signal Group/Column (0), etc., and in general, bitline interface 20p corresponds to group and column select signal Group/Column(n). The individual memory cells of a column are selected by wordlines 28a-28r in the conventional fashion.
Portions of the read path circuitry for memory device 10 are also illustrated in FIG. 1. Bitline signals from a pair of bitlines BL and BL are received by sense amplifiers 30a-30l. In response to corresponding Group.sub.-- Enable signals, the sense amplifiers 30a-30l generate signals Data.sub.-- Out which are provided to a global read data bus. In some cases, the global read data bus may be the same bus as the global write data bus 22. The Data.sub.-- Out signals on the global read data bus may be provided to further circuitry to generate the output signals which are provided to the I/O pads (e.g., I/O pad 12).
In general, SRAMs such as memory device 10 illustrated in FIG. 1 have been required to provide faster and faster access times to accommodate ever increasing processor and bus speeds. This has led to decreased write cycle times for memory devices, which generally translate to a narrower internal write pulse (datawrt0 or datawrt1). However, in co-pending application Ser. No. 08/855,040 entitled "A Method and Circuit for Enhancing Write Parameter Margins in a Memory Device", filed May 13, 1997, now U.S. Pat. No. 5,825,715, issued Oct. 20, 1998 by Stefan-Cristian Rezeanu, and assigned to the assignee of the present invention, the entire disclosure of which is hereby incorporated by reference, it was shown how the timing of the internal data write pulse impacts several write parameters. To overcome these problems, it was further shown how several write parameter (e.g., address set-up T.sub.sa and address hold T.sub.ha) margins could be enhanced by the use of an apparatus which prevents memory writes to undesired locations by blocking the write using an address transition detection (ATD) signal. The apparatus is preferably implemented in a data write bus-to-bitline interface, for example, using passgates (gated by the ATD signal) to control access to a pair of bitlines by a data write bus. In this way, improved write parameter margins are achieved without having to rely on narrowing the internal write pulse.
Another challenge facing the designers of modern SRAMs concerns the use of increased bit-size internal word-format designs. In the past, fast CMOS SRAMs were typically implemented as 8-bit word-format components (so-called x8 parts). However, it is now becoming more common to implement large SRAMs as x16 and larger word-format parts. With the use of such larger internal word-formats comes the use of increased numbers of signals to control write operations in such parts. For example, older x8 parts often relied solely on one or two control signals (e.g., the write enable (WE) and/or chip enable (CE) signals shown in FIG. 1) to generate an internal write signal (e.g., signal Internal.sub.-- Write in FIG. 1) which could then be used to gate an internal data signal. However, larger internal word-format parts often utilize additional signals (e.g., byte high enable (BHE) and byte low enable (BLE) are a common choice for x16 parts) to generate the internal write signal. The control of write operations in such a memory device while still preserving the write parameter margins for the device is addressed by the present invention.